Short channel insulated-gate static induction transistor and method of manufacturing the same

ABSTRACT

The ultra high-speed vertical short channel insulated-gate static induction transistor with uniform operating characteristic which has the drain layer  3  consisting of an epitaxial single crystal layer on the main surface  2  of substrate  1 , the channel layer  4  with thickness 1000 Å or less on the drain layer, the source layer  5  consisting of an epitaxial single crystal layer on the channel layer  4 , and the insulated-gates  6  and  7  on the sidewalls of the drain, the channel, and the source layers. Since the thickness of 1000 Å or less is accurately controlled using the molecular layer epitaxial method and the channel layer  4  is grown up, the X-ray photolithography is not needed. Since the gate oxide film is formed by low temperature CVD using active oxygen, impurity re-distribution does not occur.

TECHNICAL FIELD

The present invention relates to a short channel insulated-gate staticinduction transistor having a high operation speed, especially, avertical and a planar type short channel insulated-gate static inductiontransistor, and a method of manufacturing the same.

BACKGROUND ART

The insulated-gate static induction transistor has been used for highfrequency amplifiers and integrated circuits which has the required highdriving capability and the high operation speed. The insulated-gatestatic induction transistor was proposed by Jun-ichi Nishizawa who isone of the inventors of the present invention, and was published, forexample, in JP,58-56270B, and JP,H3-00792B, etc. The insulated-gatestatic induction transistor and the insulated-gate transistor (MOStransistor, for example) are equivalent in that these have a source, achannel, and a drain, and currents flowing in them are controlled by agate voltage, however their operation principles are different. That is,a potential barrier in the insulated-gate static induction transistor isformed by the gate voltage and the number of carriers traveling from thesource to the drain are controlled by this potential barrier, on thecontrary, in the insulated-gate transistor a semiconductor surfacecarrier density of an interface between a semiconductor surface and agate insulator layer is changed by the gate voltage, and then the numberof carriers traveling from the source to the drain is controlled by thegate voltage.

The insulated-gate static induction transistor is so designed that theeffect of the drain electric field can have an influence on the source,and the current can be flown not only in the semiconductor-insulatorinterface but also inside of the substrate, so that it has suchoutstanding properties as an unsaturated current voltagecharacteristics, a high current driving capability, and a high speedperformance etc.

However, the demand for an improvement of a data processing speed ismore and more unlimited, and a further improvement in speed will berequired for also in the insulated-gate static induction transistor. Inorder to increase the speed of the insulated-gate static inductiontransistor and the insulated-gate transistor, it is effective to shortena channel length, the development of the insulated-gate transistor whichhas the cannel length of 1000 Å or less is progressing for a massproduction, and also the channel length below the level of several 100 Åare being developed.

However, the depletion layer of the source and that of the drainapproach or connect each other when a channel becomes shorter andshorter, it has such an intrinsic restriction in operation that currentsin a short channel insulated-gate transistor become uncontrollable bythe gate voltage. In the manufacturing method of an insulated-gatetransistor using photolithography to form a short channel, a channellength of the insulated-gate transistor is determined by a lightwavelength of photolithography, and then the shorter wavelength of thelight source, i.e. an X-ray, is required to realize a channel length of1000 Å or less. It is difficult to focus or bend an optical path of anX-ray, therefore an X ray lithography apparatus is large and its cost isexpensive, and also safety precautions to workers' to prevent an X-rayradiation exposure are indispensable.

As just described, a short channellization of an insulated-gatetransistor is not making advances. Although an electron device based onan entirely new principle of an operation, for example, the devicecalled a single electron transistor has been proposed, it does not gobeyond the research. As will be understood from the foregoingdescription, a potential barrier is formed by the gate voltage and thenumber of carriers traveling from the source to the drain is controlledby it as the principle of operation in the insulated-gate staticinduction transistor, such a phenomenon does not occur that thedepletion layer of the source and that of the drain connect each other,and hence the current becomes uncontrollable, and so it does not produceany restriction at all in the short channel insulated-gate staticinduction transistor.

And, when the molecular layer epitaxy method (see, for example, U.S.Pat. No. 5,294,286), which was invented by Dr. Jun-ichi Nishizawa et. alwho is one of the inventors of the present invention, is used, a shortchannel can be grown with precision as accurate as single molecularlayer without using the X-ray lithography apparatus.

Thus, the insulated-gate static induction transistor is highlighted as anext-generation ultra high-speed electron device.

Next, a prior art insulated-gate static induction transistor will beexplained. FIG. 8 illustrates the manufacturing method and the structureof the prior art insulated-gate static induction transistor, and itsmanufacturing process is as follows. First, as shown in FIG. 8 (a), anepitaxial layer 52 is grown as a channel on a semiconductor substrate51, and then a projection portion 52 is formed by using anisotropicetching. As shown in FIG. 8 (b), the masking is carried out using afield oxide film 53, and a gate oxide film 54 is formed in the portionof a device fabrication region.

Next as is shown in FIG. 8 (c), the polycrystalline semiconductor as fora gate electrode 55 is deposited and etched to form a gate electrode ona sidewall of the projection region 52 by the anisotropic etching, and adrain 56 and a source 57 are formed by the ion implantation using a gateelectrode 55 as a mask.

And as shown in FIG. 8 (d), a passivation film 58 is deposited, holesare opened onto the passivation film 58 for electrodes, a drainelectrode 56′ and a source electrode 57′ are formed, and finally anannealing process for impurity activation is carried out.

In the structure of the insulated-gate static induction transistormentioned above, the high temperature processes for the activation ofthe ion implanted impurities and for the gate oxide layer formation areindispensable, then impurities are distributed during these hightemperature processes, and especially the impurities of the drain 56were diffused into the channel 52 to shorten the channel length. When achannel length of the device becomes as same as the diffusion length ofimpurities, it is varied by every impurity diffusion process, a problemhas been associated as a consequence that an operation characteristicsis changed for each transistor.

Although the height of the projection part 52 may be influenced to thelength of a channel, the accuracy of the anisotropic etching can notcorrespond to the channel length of 1000 Å or less, and, for thisreason, a problem has been encountered that the insulated-gate staticinduction transistor of a certain channel length cannot be manufacturedwith a sufficient accuracy and with a good reproducibility.

At the same time, in this structure of the insulated-gate staticinduction transistor as shown in FIG. 8 (d), the gate electrode 55 andthe gate oxide film 54 are contacted with not only the channel 52 butalso the drain 56 and the source 57. For this reason, parasiticcapacitances are generated among the gate electrode 55, the drain 56 andthe source 57, so the problem has been encountered that an operationspeed of the device is limited by these parasitic capacitancesespecially when a short channel is formed.

Considering the above described problems, the primary object of thepresent invention is to provide an ultra high-speed vertical type shortchannel insulated-gate static induction transistor with a uniformoperating characteristics which has a short channel length of 1000 Å to100 Å.

Furthermore, the second object of the present invention is to provide anultra high-speed planar type short channel insulated-gate staticinduction transistor with a channel length from 1000 Å to 100 Å and withthe parasitic capacitance as small as to the limit.

And, furthermore, the third object of the present invention is toprovide their manufacturing methods of the same.

DISCLOSURE THE INVENTION

In order to achieve the first object mentioned above, there is providedin accordance with the present invention thereof a vertical type shortchannel insulated-gate static induction transistor: comprising a drainlayer consisting of an epitaxial single crystal layer on a main surfaceof a substrate, a channel layer consisting of an epitaxial singlecrystal layer of thickness 1000 Å or less on said drain layer, and asource layer consisting of an epitaxial single crystal layer on saidchannel layer, and an insulated-gate being formed on the sidewall ofsaid drain layer, said channel layer, and said source layer.

According to the structure mentioned above, since the channel layerconsists of the epitaxial single crystal layer with thickness ofhigh-accuracy, the accuracy of channel length is high, and therefore theoperating characteristics becomes uniform with no variance amongtransistors. Since the thickness of the channel layer is 1000 Å or lessand the transit time of carriers between the source and the drain isshort, therefore an ultra high operation speed can be obtained.

In the structure mentioned above, preferably, said substrate is a Sisingle crystal, said main surface is a (100) or its equivalent plane,said channel layer is a p type Si epitaxial single crystal layer, saidsource layer and said drain layer are n type Si epitaxial single crystallayers, and said insulated-gate consists of the SiO₂ and thepolysilicon.

And, in the structure mentioned above, preferably, said substrate is Sisingle crystal, said main surface is a (100) or its equivalent plane,said channel layer is n type Si epitaxial single crystal layer, saidsource layer and said drain layer are p type Si epitaxial single crystallayers, and said insulated-gate consists of the SiO₂ and thepolysilicon.

According to these structures, the vertical type short channelinsulated-gate static induction transistor can be manufactured by the Sisemiconductor technology which is the most widely used.

In order to achieve the second object mentioned above, there is providedin accordance with the present invention thereof a type short channelinsulated-gate static induction transistor comprising: a channel layerof channel length 1000 Å or less, a source layer, a drain layer beingarranged in parallel with a main surface of a substrate, characterizedin that an insulated-gate in which width is as nearly same as that ofchannel length is provided right on a channel layer.

According to this structure, the transit time of carriers between thesource and the drain is short because the channel length is short, andthere arises no parasitic capacitance since the insulated-gate has awidth as same as that of the channel length, and therefore, the ultrahigh operation speed can be attained.

In the structure mentioned above, preferably, said substrate is a Sisingle crystal, said main surface is a (100) or its equivalent plane,said channel layer is a p type Si single crystal layer, said sourcelayer and said drain layer are n type Si single crystal layers, and saidinsulated-gate consists of the SiO₂ and the polysilicon.

And, in the structure mentioned above, preferably, said substrate is Sisingle crystal, said main surface is a (100) or its equivalent plane,said channel layer is a n type Si single crystal layer, said sourcelayer and said drain layer are p type Si single crystal layers, and saidinsulated-gate consists of the SiO₂ and the polysilicon.

According to these structures, the planar type short channel insulationgate static induction transistors can be manufactured by the Sisemiconductor technology which is the most widely used.

In order to achieve the third object mentioned above, there is providedin accordance with the present invention thereof a method ofmanufacturing a vertical type short channel insulated-gate staticinduction transistor comprising the steps of: growing a drain layerepitaxially on a main surface of a semiconductor substrate with aspecific plane direction; growing a channel layer by controllingepitaxial growth of every mono molecular layer consisting of the channelon said drain layer; depositing a passivation film on said source layer;opening holes in said passivation film and forming a U-shaped grooveperpendicular to said main surface to the depth to said semiconductorsubstrate; depositing a gate oxide film on said U-shaped groove;depositing a gate electrode layer on said gate oxide film, and aninsulated-gate consisting of said gate oxide film and said gateelectrode being formed by leaving said gate oxide film layer and saidgate electrode layer on a sidewall of said U-shaped groove.

According to the method of the manufacturing mentioned above, it is madepossible to fabricate the vertical type insulated-gate static inductiontransistor with the gate length of 1000 A or less with a high accuracywithout using the X-ray photolithography.

In the method of the manufacturing mentioned above, said process to growa channel layer by controlling epitaxial growth of every mono molecularlayer are comprising the steps of: exposing said semiconductor substratesurface set in a vacuum vessel to a compound gas of a semiconductorelement and evacuating a certain time, and after this exposing andevacuating, exposing said surface to a compound gas of a dopant elementfor a certain time and evacuating a certain time, and repeating thesetwo steps alternately.

According to the method of the manufacturing mentioned above, it is madepossible to form the channel length from 1000 Å to 100 Å with ease and ahigh accuracy, because it is possible to form the channel layer by monomolecular layer accuracy by controlling the number of cycles comprisingsaid two steps. Also, since a single crystal film is epitaxially grownby said cycles, such a high temperature thermal treatment for animpurity activation etc. is not necessary.

In the method of the manufacturing mentioned above, said process to formsaid U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface.

According to the method of the manufacturing mentioned above, theU-shaped groove having vertical sidewall perpendicular to said mainsurface can be formed, and consequently it enables to form saidinsulated-gate perpendicular to said channel layer.

In the method of the manufacturing mentioned above, said process todeposit said gate oxide film is a low temperature CVD in which acompound gas of a semiconductor element and an active oxygen gas reacton a surface of said semiconductor substrate.

According to the method of the manufacturing mentioned above, the lengthof the channel can be controlled to the designed specification, sincethe impurities of the channel layer, the source layer, and the drainlayer are not redistributed.

In the method of the manufacturing mentioned above, said process todeposit said gate electrode layer is a low temperature CVD to depositpolycrystalline semiconductor by decomposing the compound gas of asemiconductor element on a surface of said semiconductor substrate.

According to the method of the manufacturing mentioned above, asufficient thickness of the gate electrode layer can also be depositedon the sidewall of the U-shaped groove.

In the method of the manufacturing mentioned above, said process toleave said gate oxide film layer and gate electrode layer on thesidewall of U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface, andsaid gate oxide film layer and gate electrode layer is left on thesidewall of U-shaped groove by an etching of using of thicknessdifference between the thickness in the direction perpendicular to saidmain surface and the film thickness.

According to the method of the manufacturing mentioned above, it is madepossible to leave the gate electrode and the gate oxide film only on thesidewall by controlling the etching time, since the gate electrodedeposited on the sidewall of U-shaped groove is thick in the directionperpendicular to the main surface.

In the method of the manufacturing mentioned above, said compound gas ofa semiconductor element is Si₂H₆ (disilane). And said compound gas of adopant element is preferably PH₃ (phosphine) in case of an n typedopant, and B₂H₆ (diborane) in case of a p type dopant.

According to the method of the manufacturing mentioned above, a p type,a n type, and an i type channel can be formed.

In order to achieve the third object mentioned above, there is alsoprovided in accordance with the present invention thereof a method ofmanufacturing a planar type short channel insulated-gate staticinduction transistor comprising the steps of: growing a drain layerepitaxially on a main surface of a semiconductor substrate with aspecific plane direction; depositing a passivation film on said drainlayer; making openings of said passivation film and forming a U-shapedgroove in the direction perpendicular to said main surface to the depthto said semiconductor substrate; growing a channel layer and a sourcelayer by controlling epitaxial growth of every mono molecular layer ontosaid U-shaped groove; depositing a gate oxide film on said channel layerand said source layer grown on said main surface, depositing a gateelectrode layer on said gate oxide film, and an insulated-gateconsisting of said gate oxide film and said gate electrode being formedby leaving said gate oxide film layer and said gate electrode layer onsaid sidewall of said U-shaped groove.

According to the method of the manufacturing mentioned above, it is madepossible to manufacture the planar type short channel insulated-gatestatic induction transistor having a gate length of 1000 Å or less witha high accuracy without using the X-ray photolithography.

In the method of the manufacturing mentioned above, said process to formsaid U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface.

According to the method of the manufacturing mentioned above, saidU-shaped groove having a sidewall perpendicular to said main surface canbe made, and consequently, a source layer, a channel layer, and a drainlayer can be arranged in parallel with said main surface of saidsemiconductor substrate.

In the method of the manufacturing mentioned above, said process to growsaid channel layer and said source layer by controlling epitaxial growthof every mono molecular layer onto said U-shaped groove comprises fromthe steps of exposing said semiconductor surface set in a vacuum vesselto a compound gas of a semiconductor element and evacuating a certaintime, and after this step, exposing said semiconductor surface to acompound gas of a dopant element and evacuating a certain time, andrepeating these two steps alternately.

According to the method of the manufacturing mentioned above, it is madepossible to form the channel of the length from 1000 Å to 100 Å withease and a high accuracy, and also it is made possible to grow only onthe sidewall and on the bottom of said U-shaped groove because of thelow process temperature. Also, since a single crystal film is grown insaid cycles, such a high temperature thermal treatment for an impurityactivation etc. is not necessary.

In the method of the manufacturing mentioned above, said process todeposit said gate oxide film is a low temperature CVD in which acompound gas of a semiconductor element and an active oxygen gas reacton a surface of said semiconductor substrate so as to grow said gateoxide film.

According to the method of the manufacturing mentioned above, the lengthof the channel can be controlled to the designed specification, sincethe impurities of the channel layer, the source layer, and the drainlayer are not redistributed, because of said low temperature process.

In the method of the manufacturing mentioned above, said process todeposit said gate electrode layer is a low temperature CVD to depositpolycrystalline semiconductor by decomposing the compound gas of asemiconductor element on a surface of said main surface.

According to the method of the manufacturing mentioned above, asufficient thickness of the gate electrode layer can be deposited on thesidewall of the U-shaped groove.

In the method of the manufacturing mentioned above, said process toleave said gate oxide film layer and gate electrode layer on thesidewall of U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface, andsaid gate oxide film layer and gate electrode layer is left only on thesidewall of U-shaped groove by an etching of using of thicknessdifference between the thickness in the direction perpendicular to saidmain surface and the film thickness.

According to the method of the manufacturing mentioned above, it is madepossible to leave the gate electrode and the gate oxide film to a widthas same as that of channel length and just above on said channel.

In the method of the manufacturing mentioned above, said semiconductorsubstrate with a specific oriented plane is a Si (100) or its equivalentplane.

According to the method of the manufacturing mentioned above, it ispossible to select a (010) or its equivalent plane as the sidewallsurface of U-shaped groove, and also it is possible to select a <010> orits equivalent direction as the arrangement direction of the source, thechannel, and the drain. By selecting a (010) or its equivalent plane asthe sidewall surface of U-shaped groove, it is made possible to growsaid channel layer selectively on the sidewall of said U-shaped groove.

In the method of the manufacturing mentioned above, said compound gas ofa semiconductor element is Si₂H₆ (disilane). And said compound gas of adopant element is PH₃ (phosphine) in case of an n type dopant, and B₂H₆(diborane) in case of a p type dopant.

According to the method of the manufacturing mentioned above, a p type,a n type, and an i type channel can be formed.

BRIEF DESCRIPITION OF THE DRAWINGS

The present invention will better be understood from the followingdetailed description and the drawings attached hereto showing certainillustrative forms of embodiment of the present invention; in thisconnection, it should be noted that such forms of embodiment illustratedin the accompanying drawings hereof are intended in no way to limit thepresent invention but to facilitate an explanation and an understandingthereof, in which drawings:

FIG. 1 shows a structure of a vertical type short channel insulated-gatestatic induction transistor of the present invention;

FIG. 2 shows a structure of a planar type short channel insulated-gatestatic induction transistor of the present invention;

FIG. 3 shows a method of manufacturing a vertical type short channelinsulated-gate static induction transistor of the present invention;

FIG. 4 shows a method of manufacturing and a structure of a low powerconsumption vertical type short channel insulated-gate static inductiontransistor manufactured by a method of the present invention;

FIG. 5 shows a method of manufacturing and a structure of the verticaltype short channel insulated-gate static induction transistormanufactured by a method of the present invention on an SOI substrate;

FIG. 6 shows a method of manufacturing a planar type short channelinsulated-gate static induction transistor of the present invention;

FIG. 7 shows a structure of a tunnel injection type insulated-gatestatic induction transistor manufactured by a method of the presentinvention;

FIG. 8 shows a method of manufacturing and the structure of a prior artinsulated-gate static induction transistor.

BEST MODES FOR CARRYING OUT THE INVENTION

Hereinafter, an explanation is given in respect of a vertical type shortchannel insulated-gate static induction transistor, a planar type shortchannel insulated-gate static induction transistor, and the methods ofmanufacturing thereof as suitable forms of embodiment of the presentinvention, references being made to FIGS. 1 to 7. Here the substantiallysame parts are given same reference numerals.

A vertical type short channel insulated-gate static induction transistorof this invention is explained first.

FIG. 1 is a diagrammatic sectional view showing a structure of avertical type short channel insulated-gate static induction transistorof the present invention.

As shown in FIG. 1, a vertical type short channel insulated-gate staticinduction transistor of the present invention has a semiconductorsubstrate 1, and a drain layer 3 which is an epitaxial single crystallayer on a main surface 2 of a semiconductor substrate 1, a channellayer 4 which is an epitaxial single crystal layer with specificthickness of 1000 Å or less on the drain layer 3, and a source layer 5which is an epitaxial single crystal layer on the channel layer 4, andit also has a gate oxide film 6 and a gate electrode 7 on the sidewallof the drain layer 3, the channel layer 4, and the source layer 5, andthe drain electrode 3′ at the end of the drain layer 3 and the sourceelectrode 5′ right above the source layer 5, respectively, and theinsulated passivation film 8′ to insulate and support these electrodes.

The semiconductor substrate 1, for example, is Si single crystal, themain surface 2 is (100) or its equivalent plane, the channel layer 4 isa p type Si epitaxial single crystal layer, a drain layer 3 and a sourcelayer 5 are an n type Si epitaxial single crystal layers, and the gateoxide film 6 and the gate electrode 7 are the SiO₂ and the polysilicon,respectively. The channel layer 4 may be an n type Si epitaxial singlecrystal layer, and the drain layer 3 and the source layer 5 may be a ptype Si epitaxial single crystal layers.

According to the above described structure of the vertical type shortchannel insulated-gate static induction transistor of the presentinvention, its carrier transit time between the source and the drain canbe made possible to be very short by virtue of its extremely shortchannel length. And also, the accuracy of channel length is veryprecise, since the channel layer is determined by the thickness of theepitaxial single crystal layer.

Next, a planar short type channel insulated-gate static inductiontransistor of the present invention will be explained. FIG. 2 is adiagrammatic sectional view, showing a structure of a planar type shortchannel insulated-gate static induction transistor of the presentinvention.

FIG. 2 shows a sectional view perpendicular to a main surface of asubstrate in the arrangement direction to a source layer, a channellayer, and a drain layer. In FIG. 2, a planar type short channelinsulated-gate static induction transistor of the present invention hasa semiconductor substrate 1, a drain layer 3, a channel layer 4 having achannel length less than 1000 Å, and a source layer 5. Said drain layer3, said channel layer 4, and said source layer 5 are so arranged tocontact mutually and in parallel with a main surface 2 of saidsemiconductor substrate 1, and their heights i.e. thickness in thedirection perpendicular to said main surface 2 are the same. It also hasa gate oxide film 6 and a gate electrode 7 of the width approximatelyequal to the channel length L right above the channel layer 4, and theinsulated-gate comprises of the gate oxide film 6 and the gate electrode7. It also has a drain electrode 3′ and a source electrode 5′ rightabove the drain layer 3 and the source layer 5, respectively, and has aninsulated passivation film 8 and 8′ to insulate and support theseelectrodes.

And, for example, the semiconductor substrate 1 is a Si single crystal,its main surface 2 is a (100) or its equivalent plane, the channel layer4 is a p type Si single crystal layer, the drain layer 3 and the sourcelayer 5 are an n type Si single crystal layers, and the gate oxide film6 and the gate electrode 7 are SiO₂ and the polysilicon, respectively.The channel layer 4, for example, may be an n type Si single crystallayer, and the drain layer 3 and the source layer 5 may be a p type Sisingle crystal layer.

According to the above described structure of the planar type shortchannel insulated-gate static induction transistor of the presentinvention, its carrier transit time between the source and the drain canbe made possible to be very short by virtue of its extremely shortchannel length.

And the width of the insulated-gate which is consisted by the gate oxidefilm 6 and the gate electrode 7 is almost equal to the channel length L,there does not arise a capacitance, i.e., parasitic capacitanceunnecessary for an device operation, and therefore a very high operationspeed can be realized.

The operation speed of the THz band is possible by the planar type shortchannel insulated-gate static induction transistor of the presentinvention due to above described effect.

Next, a method of manufacturing a vertical type short channelinsulated-gate static induction transistor of the present invention willbe explained as embodiment 1. FIG. 3 is a diagrammatic view showing amethod of manufacturing a vertical type short channel insulated-gatestatic induction transistor of the present invention.

As shown in FIG. 3(a), a drain layer 3 is grown epitaxially on the mainsurface 2 of a Si substrate 1 with (100) oriented plane. The drain layer3 may be formed by introducing impurities into the Si substrate 1 byeither a thermal diffusion or an ion implantation. Next, a channel layer4 is grown epitaxially on the drain layer 3. In order to realize achannel length of 1000 Å to 100 Å accurately, the molecular layerepitaxy (see, for example, U.S. Pat. No. 5,294,286) is used for theepitaxial growth of the channel layer 4.

The Si substrate 1 with the drain layer 3 formed on it is set in avacuum vessel for the molecular layer epitaxy, for example to form thechannel layer 4 of n type impurity concentration n=3×10¹⁹ cm⁻³, Si₂H₆gas is introduced into a vacuum vessel at crystal growth temperature510° C., the substrate 1 is exposed for 30 seconds to Si₂H₆ gas at apressure of 4×10⁻² Pa, then Si₂H₆ gas is evacuated for 2 seconds, andthen PH₃ gas is introduced into the vacuum vessel, the substrate isexposed for 10 seconds to PH₃ gas at a pressure of 5×10⁻⁶ Pa, then PH₃gas is evacuated for 2 seconds. By carrying out one cycle of the abovementioned process as a unit cycle, mono molecular epitaxial layer whichconsists of a Si single crystal of n type impurity concentration ofn=3×10¹⁹ cm⁻³ is grown, and by repeating the cycle by the number oftimes corresponding to the number of molecular layers of the channellayer 4, the desired film thickness of the channel layer 4 is grown.

The grown film thickness by the above mentioned unit cycle is 1.15 Å ona silicon (001) or its equivalent plane, and this film thicknesscorresponds to 85% of the thickness of mono atomic layer. Thus, thesilicon single crystal layer thickness of 1.15 Å can be grown by eachcycle. That is, in order to form the channel length of 100 Å, the abovementioned cycle should be repeated about 85 times.

In order to form the channel layer 4 of a p type impurity concentrationp=1×10²⁰ cm⁻³ for example, the above mentioned substrate is exposed for30 seconds to Si₂H₆ gas at a pressure of 4×10⁻² Pa by introducing Si₂H₆gas into a vacuum vessel at the crystal growing temperature 510° C.,then Si₂H₆ gas is evacuated for 2 seconds, and exposed for 10 seconds toB₂H₆ gas at a pressure of 5×10⁻⁵ Pa by introducing B₂H₆ gas into thevessel, then B₂H₆ gas is evacuated for 2 seconds. By repeating cycles ofthe above mentioned process as a unit cycle, the channel layer 4 whichconsists of a Si single crystal of a p type impurity concentration ofp=1×10²⁰ cm⁻³ and has a desired thickness is grown.

In order to grow a non-doped Si single crystal, the above mentionedsubstrate is exposed for 30 seconds to Si₂H₆ gas at a pressure of 4×10⁻²Pa by introducing Si₂H₆ gas into a vacuum vessel, then Si₂H₆ gas isevacuated for 2 seconds. By repeating cycles of above mentioned processas a unit cycle, the non-doped single crystal Si layer which has desiredfilm thickness is grown up.

Next, the source layer 5 is grown epitaxially. Needless to say that theepitaxial drain layer 3 and the source layer 5 may be grown by usingeither the above mentioned molecular layer epitaxy or the conventionalepitaxial growth techniques. The doping density of the source layer 5and the drain layer 3 is about 10¹⁸ to 10²¹ cm⁻³. It is needless to saythat the conduction type may be either p or n type, and 5 may be thedrain and 3 may be the source.

The impurity concentration of the channel layer 4 is about 10¹⁶ to 10²¹cm⁻³, and its conduction type is opposite to those of the source 5 andthe drain 3. The channel layer 4 may be a multilayer structure, such asan i-p-i structure which sandwiches the p layer with non-doped i layers.The vertical type short channel insulated-gate static inductiontransistor having i-p⁺-i multilayer structure of total channel length of100 Å in which film thickness is 40 Å, 20 Å, and 40 Å, respectively, wasfabricated experimentally and its good operation performance wasconfirmed.

In FIG. 3 (b) is shown, a passivation film 8 is deposited, thepassivation film 8 is removed partially to make the opening in theportion of the device forming region by etching to the directionperpendicular to the main surface 2 of the Si substrate 1 by using theanisotropic plasma etching or the like, and thus a U-shaped groove 10with a sidewall 9 consisting of the passivation film 8, the source layer5, the channel layer 4, and the drain layer 3, which is perpendicular tothe main surface 2, is formed. In the figure, only a half of theU-shaped groove 10 is illustrated.

The plasma etching using PCl₃ (phosphorus trichloride), for example, isused for the anisotropic plasma etching. The depth of the U-shapedgroove 10 may be such that it reaches to the drain layer 3, or theinside of the drain layer 3.

Next, the gate oxide film layer 6 is deposited on the substrate in whichthe U-shaped groove 10 has been formed. In order to lower thetemperature at the time of gate oxide film layer 6 formation, it shouldbe formed by using low temperature plasma CVD method using Si₂H₆ and anactive oxygen, and SiO₂ is deposited to the thickness of 20 to 100 Å. Anexample of deposition condition is such that the substrate temperatureis 470° C., Si₂H₆ gas pressure is 7×10⁻² Pa, the active oxygen gaspressure is about 10⁻¹ Pa, and the power of plasma supply is 200 W.

As shown in FIG. 3 (c), a polysilicon layer 7 which will function as agate electrode is deposited onto the substrate with the gate oxide filmlayer 6 deposited on it. The polysilicon layer 7 is deposited to thethickness of about 500 to 5000 Å by using low temperature plasma CVDmethod with Si₂H₆.

Next, the gate electrode 7 and gate oxide film 6 are formed by etchingthe deposited polysilicon layer 7 and the deposited oxide film layer 6using the anisotropic plasma etching. The anisotropic plasma etching iscarried out by using PCl₃ gas at a pressure of 3 to 30 Pa. Thisanisotropic plasma etching has a high etching speed in the directionperpendicular to the main surface of Si substrate 1. Since the thicknessin the direction perpendicular to the main surface 2 of the sidewall 9of the polysilicon layer 7 is thicker as the thickness of passivationfilm 8 than the film thickness of the polysilicon layer 7, aninsulated-gate consisting of the gate oxide film 6 and the gateelectrode 7 can be left only on the sidewall 9 by selecting the etchingtime when the thickness of the polysilicon corresponding to the filmthickness of passivation film 8 is etched out.

Next, as shown in FIG. 3 (d), the whole process is completed bydeposition of the passivation film 8′ on the substrate in which theinsulated-gate was formed, and then by forming the source electrode 5′and the drain electrode 3′ after opening contact holes.

According to this manufacturing method mentioned above, the verticaltype short channel insulated-gate static induction transistor can bemanufactured by the Si semiconductor technology which is now most widelyused.

The vertical type short channel insulated-gate static inductiontransistor with a gate length 1000 Å or less can be fabricated with ahigh accuracy without using X-ray photolithography.

The insulated-gate can be formed perpendicular to the channel layer,since the U-shaped groove with vertical sidewall can be formed.

Also, the channel of length from 1000 Å to 100 Å can be formed with easeand a high accuracy, since it is grown by the molecular layer epitaxy.

And, also the process temperature to deposit the gate oxide film byusing low temperature CVD is low, so that the channel length can becontrolled to the designed value, since the impurities in the channellayer, the source layer, and the drain layer are not redistributed.

In addition, the channel length is not changed, and the impurities arenot re-distributed, since the process to deposit the gate electrodelayer is a low temperature CVD process.

The gate electrode and the gate oxide film can be left on the sidewallportion, since the gate electrode is etched by the method mentionedabove, namely by the self aligned anisotropic etching.

The embodiment 2 will be explained next. FIG. 4 shows a method ofmanufacturing and a structure of a low power consumption vertical typeshort channel insulated-gate static induction transistor manufactured bythe method of the present invention.

As shown in FIG. 4(b), the only difference from the embodiment 1 isdepositing a sidewall channel layer 31 just before a deposition of gateoxide film layer 6. The sidewall channel layer 31 is the non-dopedsilicon epitaxial single crystal layer of impurity concentration rangedfrom 10¹² to 10¹⁶ cm⁻³ grown to a thickness of 20 to 100 Å by using themolecular layer epitaxy. This transistor can reduce the leakage currentaccompanied with short channellization at OFF state of the transistor,and therefore can reduce the STANDBY power without lowering itsoperation speed by the suitable adjustment of the impurity concentrationof the sidewall channel 31 and the channel layer 4 on the bulk side.

Next, the embodiment 3 will be explained. FIG. 5 shows a method ofmanufacturing and a structure of a vertical type short channelinsulated-gate static induction transistor formed on an SOI substratemanufactured by the method of the present invention. The SOI (Silicon onInsulator) is a substrate in which Si single crystal layer 43 is formedon SiO₂ layer 42, and SiO₂ layer 42 is formed on Si substrate 41.

As shown in FIG. 5 (a), the only difference from the embodiment 1 isusing a Si single crystal layer 43 of the SOI substrate as the drainlayer. The parasitic capacitance of the gate decreases and the operationspeed is further improved since the vertical type short channelinsulated-gate static induction transistor formed on the SOI substratehas a good electrical isolation between the substrate and the devicelayer. It also has another effects, such as improvements of insulationbreakdown voltage and the radiation tolerance characteristics in thedevice, so the device can be used for the integrated circuits and thelike for which a high environmental reliability is required.

Next, the method of manufacturing the planar type short channelinsulated-gate static induction transistor of the present invention willexplained using the embodiment 4. FIG. 6 shows a diagrammatic view of amanufacturing method of a planar short channel insulated-gate staticinduction transistor according to the present invention.

As shown in FIG. 6 (a), a passivation film 8 of SiO₂ is formed usingchemical vapor deposition (CVD) method after forming a drain layer 3 ona main surface 2 of a Si substrate 1 having a Si (100) plane. The drainlayer 3 is formed either by introducing impurities into the substrate 1by thermal diffusion or by ion implantation, or by epitaxial growth withimpurity doping, and either one of the methods may be chosen bytechnical necessity.

As shown in FIG. 6 (b), the passivation film 8 is partially removed tomake the opening in the portion of the device forming region, an etchingis performed in the direction perpendicular to the main surface 2 of Sisubstrate 1 by the anisotropic plasma etching or the like, and aU-shaped groove 10 is formed having a sidewall 9 perpendicular to themain surface 2, which consists of the passivation film 8, the drainlayer 3, and the Si substrate 1. In the figure, only a half portion ofthe U-shaped groove 10 is illustrated.

The plasma etching using PCl₃ (phosphorus trichloride), for example, isused for the anisotropic plasma etching.

The depth of the U-shaped groove 10 may be such that it reaches to theSi substrate 1, or to the inside of the Si substrate 1.

As shown in FIG. 6 (c), a channel layer 4 and 4′ are grown epitaxiallyonto the sidewall 9 of the drain layer 3, the portion of Si substrate 1,and the bottom portion of the U-shaped groove 10, followed by selectiveepitaxial growth of the source layer 5 on the sidewall portion of thechannel layer 4′ and the bottom portion of the channel layer 4′.

The selective epitaxial growth in the above mentioned method isperformed by choice of the crystal plane direction and using themolecular layer epitaxy explained below without any auxiliary processsuch as protecting other non grown region.

The Si substrate 1 with U-shaped groove 10 formed on it is set in avacuum vessel for the molecular layer epitaxy, for example to form thechannel layer 4 of n type impurity concentration n=3×10¹⁹ cm⁻³, Si₂H₆gas is introduced into a vacuum vessel at crystal growth temperature510° C., the above mentioned substrate is exposed for 30 seconds toSi₂H₆ gas at a pressure of 4×10⁻² Pa, then Si₂H₆ gas is evacuated for 2seconds, and then PH₃ gas is introduced into the vacuum vessel, thesubstrate is exposed for 10 seconds to PH₃ gas at a pressure of 5×10⁻⁶Pa, then PH₃ gas is evacuated for 2 seconds. By repeating cycles of theabove mentioned process as a unit cycle, the channel layer 4 whichconsists of a Si single crystal of n type impurity concentration ofn=3×10¹⁹ cm⁻³ and has the predetermined film thickness, is grown.

The grown film thickness by the above mentioned unit cycle is 1.15 Å ona silicon (001) or its equivalent plane, and this film thicknesscorresponds to 85% of the thickness of mono atomic layer. Thus, thesilicon single crystal layer thickness of 1.15 Å can be grown by theeach cycle. The silicon single crystal film of 1.15 Å thickness can begrown by the each cycle on the drain layer 3 of the sidewall 9 and onthe Si substrate 1, if the plane direction of Si substrate 1 and thearrangement direction of the source layer 3, the channel layer 4, andthe drain layer 5 are chosen so that the plane of the drain layer 3 ofthe sidewall 9 is (001) or its equivalent. That is, in order to form thechannel length of 100 Å, the above mentioned cycle should be repeatedabout 85 times.

Under this growth condition, silicon is not deposited at all onto thepassivation film 8, but is grown selectively onto the drain layer 3 ofthe sidewall 9 and the Si substrate 1.

In order to form the source layer 5 of a p type impurity concentrationp=1×10²⁰ cm⁻³ for example, the above mentioned substrate is exposed for30 seconds to Si₂H₆ gas at a pressure of 4×10⁻² Pa by introducing Si₂H₆gas into a vacuum vessel at the crystal growing temperature 510° C.,then Si₂H₆ gas is evacuated for 2 seconds, and then exposed for 10seconds to B₂H₆ gas at a pressure of 5×10⁻⁵ Pa by introducing B₂H₆ gasinto the vessel, then B₂H₆ gas is evacuated for 2 seconds. By repeatingthe cycle of above mentioned process as a unit cycle, the source layer 5which consists of a Si single crystal of a p type impurity concentrationof p=1×10²⁰ cm⁻³ and has a predetermined film thickness, can be grown.

In order to grow a non-doped Si single crystal, the above mentionedsubstrate is exposed for 30 seconds to Si₂H₆ gas at a pressure of 4×10⁻²Pa by introducing Si₂H₆ gas into a vacuum vessel, and then Si₂H₆ gas isevacuated for 2 seconds. By repeating cycles of above mentioned processas a unit cycle, the non-doped single crystal Si layer which has apredetermined film thickness can be grown.

The impurity concentration of the source layer 5 and the drain layer 3is about 10¹⁶ to 10²¹ cm⁻³. Needless to say that the conduction type maybe either p type or n type, and 5 may be the drain and 3 may be thesource. The impurity concentration of the channel layer 4 is about 10¹⁶to 10²¹ cm⁻³, and its conduction type is opposite to those of the sourcelayer 5 and the drain layer 3. Also, the channel layer 4 may be themultilayer structure, such as an i-p-i structure which sandwiches the player with non-doped i layers. The planar type short channelinsulated-gate static induction transistor having i-p⁺-i multilayerstructure of total channel length of 100 Å, in which film thickness is40 Å, 20 Å, and 40 Å, respectively, was fabricated experimentally. Andits good operation performance was confirmed.

Next, as shown in FIG. 6(d), a gate oxide film layer 6 and a polysiliconlayer 7 which will function as gate electrode is deposited. In order tolower the temperature at the formation of gate oxide film layer 6, it isformed by using low temperature plasma CVD method using Si₂H₆ gas and anactive oxygen gas, and SiO₂ is deposited to the thickness of 20 to 100Å. An example of deposition condition is such that the substratetemperature is 470° C., Si₂H₆ gas pressure is 7×10⁻² Pa, the activeoxygen pressure is about 10⁻¹ Pa, and the power of plasma supply is 200W. A polysilicon layer 7 which will function as a gate electrode isdeposited to a thickness of about 500 to 5000 Å by using low temperatureplasma CVD method with Si₂H₆ gas. According to this process asillustratively shown in FIG. 6 (d), the polysilicon 7 deposits also onthe sidewall 9.

As shown in FIG. 6 (e), the gate oxide film 6 and the gate electrode 7are formed by etching the deposited polysilicon layer 7 and oxide filmlayer 6 using the anisotropic plasma etching. The anisotropic plasmaetching is carried out by using PCl₃ gas at a pressure of 3 to 30 Pa.This anisotropic plasma etching has a high etching speed in thedirection perpendicular to the main surface 2 of Si substrate 1. Sincethe thickness of the polysilicon layer 7 on the sidewall 9 in thedirection perpendicular to the main surface 2 is thicker as a thicknessof the passivation film 8 than the film thickness of the polysiliconlayer 7, the insulated-gate consisting of the gate oxide film 6 and thegate electrode 7, which has the width approximately equal to the channellength L, can be left on the sidewall 9 and just above the channel 4, ifthe anisotropic etching with a high etching speed in the directionperpendicular to the main surface 2 is performed by controlling theetching time.

Next, the whole process is completed by deposition of a passivation film8′ on the substrate in which the insulated-gate was formed, and then byforming a source electrode 5′ and a drain electrode 3′ after openingcontact holes.

According to this manufacturing method mentioned above, the planar typeshort channel insulated-gate static induction transistor can bemanufactured by the Si semiconductor technology which is now most widelyused.

The planar type short channel insulated-gate static induction transistorwith a gate length 1000 Å or less can be fabricated with a high accuracywithout using X-ray photolithography.

The source, the channel, and the drain of the insulated-gate staticinduction transistor can be arranged in parallel with the main surfaceof the semiconductor substrate, since the U-shaped groove with verticalsidewall can be formed.

Also, since the channel is grown by the molecular layer epitaxy, thechannel of length from 1000 Å to 100 Å can be formed with ease and ahigh accuracy, and also the epitaxial channel layer can be grownselectively only onto the sidewall and bottom of the U-shaped groove. Inaddition, as a single crystal film is grown, such a high temperaturethermal treatment for an impurity activation etc. is not necessary.

And, also the process temperature to deposit the gate oxide film byusing low temperature CVD is low, so that the channel length can becontrolled to the designed value, since the impurities in the channellayer, the source layer, and the drain layer are not redistributed.

In addition, the process to deposit the gate electrode layer is a lowtemperature CVD process, so that it can be deposited on the sidewall ofthe U-shaped groove, and impurities are not re-distributed.

Further, the gate electrode and the gate oxide film having a width assame as that of the channel length can be left on the sidewall portion,since the gate electrode is etched by the self aligned anisotropicetching.

Since the substrate with Si (100) oriented plane is used and thearrangement direction of the source, the channel, and the drain is madeto <010> or <001> directions, then the plane direction of the sidewallsurface of U-shaped groove becomes (010) or (001) plane, and it is madepossible to be grown the channel layer selectively onto the sidewallsurface by virtue of using the molecular layer epitaxy.

Next, the embodiment 5 of the present invention will be explained. FIG.7 is a diagrammatic view showing a structure of the tunnel injectiontype insulated-gate static induction transistor fabricated by amanufacturing method of the planar short channel insulated-gate staticinduction transistor according to the present invention.

In this embodiment, a source layer 5 is a p⁺ doped layer, a drain layer3 is a n⁻ doped layer, and a channel layer 4 is a single crystalepitaxially grown film of a thickness 10 to 1000 Å and of a low impurityconcentration. The conduction type of the source layer and the drainlayer are the same in those of the embodiment 4, on the other hand theyare different in the structure of tunnel injection type in thisembodiment. The good device operation performance was confirmed also inthis embodiment.

Although the present invention has hereinbefore been set forth withrespect to certain illustrative forms of an embodiment thereof, it willreadily be appreciated to be obvious to a person skilled in the art thatmany alternations thereof, omissions therefrom and additions thereto canbe made without departing from the essences and the scope of the presentinvention. Accordingly, it should be understood that the invention isnot intended to be limited to the specific forms of the embodimentthereof set forth below, but to include all possible forms of theembodiment thereof that can be made within the scope with respect to thefeatures specifically set forth in the appended claims and encompassesall the equivalents thereof.

INDUSTRIAL APPLICABILITY

As will have been appreciated from the foregoing description, thepresent invention provides an ultra-high speed vertical type shortchannel insulated-gate static induction transistor with the channellength from 1000 to 100 Å, and also provides a method of manufacturingvertical type short channel insulated-gate static induction transistorof uniform operation characteristic.

Accordingly, a planar type short channel insulated-gate static inductiontransistor of the present invention and a method of manufacturing thesame, a planar type short channel insulated-gate static inductiontransistor with the channel length from 1000 to 100 Å, and withparasitic capacitance as small as to the limit, so hence of ultra-highspeed, can be provided.

If the transistors of the present invention is used for a high speedamplification circuit, a high speed integrated circuit, etc., it isquite useful as the next generation ultra high speed amplificationcircuit, an ultra high speed integrated circuit, etc.

1-3. (canceled)
 4. A planar type short channel insulated-gate staticinduction transistor comprising: a channel layer of channel length 1000Å or less; a source layer; and a drain layer, wherein said channellayer, said source layer and said drain layer being arranged in parallelwith a main surface of a substrate, and an insulated-gate in which widthis as same as that of said channel length being provided right on saidchannel layer.
 5. A planar type short channel insulated-gate staticinduction transistor as set forth in claim 4, characterized in that saidsubstrate being Si single crystal, said main surface being a (100) orits equivalent plane, said channel layer being p type Si single crystallayer, said source layer and said drain layer being an n type Si singlecrystal layer, and said insulated-gate consisting of the SiO₂ and thepolysilicon.
 6. A planar type short channel insulated-gate staticinduction transistor as set forth in claim 4, characterized in that saidsubstrate being Si single crystal, said main surface being a (100) orits equivalent plane, said channel layer being an n type Si singlecrystal layer, said source layer and said drain layer being a p type Sisingle crystal layer, and said insulated-gate consisting of the SiO₂ andthe polysilicon.
 7. A method of manufacturing a vertical type shortchannel insulated-gate static induction transistor, comprising the stepsof: growing a drain layer epitaxially on a main surface of asemiconductor substrate with a specific plane direction; growing achannel layer by controlling epitaxial growth of every mono molecularlayer on said drain layer; depositing a passivation film on said sourcelayer; making openings in said passivation film and forming a U-shapedgroove perpendicular to said main surface to the depth to saidsemiconductor substrate; depositing a gate oxide film on said U-shapedgroove; depositing a gate electrode layer on said gate oxide film, andan insulated-gate consisting of said gate oxide film and said gateelectrode being formed by leaving said gate oxide film layer and saidgate electrode layer on a sidewall of said U-shaped groove.
 8. A methodas set forth in claim 7, characterized in that said process to grow saidchannel layer by controlling epitaxial growth of every mono molecularlayer are comprising the steps of exposing said semiconductor substratesurface set in a vacuum vessel to a compound gas of a semiconductorelement for a certain time and evacuating a certain time, and thenexposing said semiconductor substrate surface to a compound gas of adopant element for a certain time and evacuating a certain time.
 9. Amethod as set forth in claim 7, characterized in that said process toform said U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface.
 10. Amethod as set forth in claim 7, characterized in that said process todeposit said gate oxide film is a low temperature CVD process in which acompound gas of a semiconductor element and an active oxygen gas reacton a surface of said semiconductor substrate.
 11. A method as set forthin claim 7, characterized in that said process to deposit said gateelectrode layer is a low temperature CVD to deposit polycrystallinesemiconductor by decomposing the compound gas of a semiconductor elementon a surface of said semiconductor substrate, wherein said gateelectrode layer is deposited also on a sidewall of said U-shaped groove.12. A method as set forth in claim 7, characterized in that said processto leave said gate oxide film layer and gate electrode layer on thesidewall of U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface,wherein said gate oxide film layer and gate electrode layer is left onthe sidewall of U-shaped groove by the etching of making use adifference of the thickness of said gate electrode layer.
 13. A methodas set forth in any one of claims 8, 10, or 11, characterized in thatsaid compound gas of a semiconductor element is Si₂H₆ (disilane).
 14. Amethod as set forth in claim 8, characterized in that said compound gasof a dopant element is PH₃ (phosphine) in case of an type dopant, andB₂H₆ (diborane) in case of a p type dopant.
 15. A method ofmanufacturing a planar type short channel insulated-gate staticinduction transistor, comprising the steps of: growing a drain layerepitaxially on a main surface of a semiconductor substrate with aspecific plane direction; depositing a passivation film on said drainlayer; making openings in said passivation film and forming a U-shapedgroove perpendicular to said main surface to the depth to saidsemiconductor substrate; growing a channel layer and a source layer onsaid U-shaped groove by controlling epitaxial growth of every monomolecular layer; depositing a gate oxide film on said channel layer andsaid source layer; depositing a gate electrode layer on said gate oxidefilm, and an insulated-gate consisting of said gate oxide film and saidgate electrode being formed by leaving said gate oxide film layer andsaid gate electrode layer on a sidewall of said U-shaped groove.
 16. Amethod as set forth in claim 15, characterized in that said process toform said U-shaped groove is an anisotropic plasma etching with a highetching speed in the direction perpendicular to said main surface.
 17. Amethod as set forth in claim 15, characterized in that said process togrow said channel layer and said drain layer by growing a channel layerand a source layer on said U-shaped groove by controlling epitaxialgrowth of every mono molecular layer comprises the steps of exposingsaid semiconductor substrate surface set in a vacuum vessel to acompound gas of a semiconductor element for a certain time andevacuating a certain time, and then exposing said semiconductorsubstrate surface to a compound gas of a dopant element for a certaintime and evacuating a certain time.
 18. A method as set forth in claim15, characterized in that said process to deposit said gate oxide filmis a low temperature CVD in which a compound gas of a semiconductorelement and an active oxygen gas react on a surface of saidsemiconductor substrate so as to grow said gate oxide film.
 19. A methodas set forth in claim 15, characterized in that said process to depositsaid gate electrode layer is a low temperature CVD to depositpolycrystalline semiconductor by decomposing the compound gas of asemiconductor element on a surface of said semiconductor substrate,wherein said gate electrode layer is deposited also on a sidewall ofsaid U-shaped groove.
 20. A method as set forth in claim 15,characterized in that said process to leave said gate oxide film layerand gate electrode layer on said sidewall of U-shaped groove is ananisotropic plasma etching with a high etching speed in the directionperpendicular to said main surface, wherein said gate oxide film layerand gate electrode layer is left on said sidewall of U-shaped groove bythe etching of making use a difference of the thickness of said gateelectrode layer.
 21. A method as set forth in claim 15, characterized inthat said semiconductor substrate with a specific oriented plane is a Si(100) substrate or its equivalent plane substrate.
 22. A method as setforth in any one of claims 17, 18 or 19, characterized in that saidcompound gas of a semiconductor element is Si₂H₆ (disilane).
 23. Amethod according to claim 17, characterized in that said compound gas ofa dopant element is PH₃ (phosphine) in case of a n type dopant, and B₂H₆(diborane) in case of a p type dopant.